The authors describe a nine-stage, pipelined, video-rate,nanalog-to-digital converter (ADC) in a 0.9-μm CMOS technology. At anconversion rate of 20 Msamples/s, the converter has 10-b resolution,n56-dB signal-to-noise-and-distortion ratio (SNDR) with a 100-kHz input,nand 54-dB SNDR with a 5-MHz input. It occupies 9.3 mm2 andndissipates 300 mW. The key innovation in this ADC is the improvedncorrection algorithm, which requires one fewer comparator per stage thannused in traditional architectures
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机译：作者介绍了一种采用0.9μmCMOS技术的九级，流水线，视频速率，模拟到数字转换器（ADC）。以20 Msamples / s的转换速率，该转换器具有10b分辨率，输入频率为100kHz时n56 dB的信噪比和失真比（SNDR），以及频率为5MHz时54dB的SNDR输入。它占据了9.3 mm 2 的能量，功耗为300 mW。该ADC的关键创新是改进的n校正算法，该算法每级所需的比较器比传统架构少
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