A Split-Based Digital Background Calibration of Pipelined Analog-to-Digital Converters by Cubic Spline Interpolation Filtering

摘要

In this paper, a digital background calibration technique for pipelined analog-to-digital converter (ADC) based on the concept of split architecture is proposed to address finite dc gain and nonlinearity of the residue amplifier. In the proposed method, the pipelined ADC divided into two channels where each channel included the first stage followed by an ideal backend ADC. A 1.5 bit per stage is chosen for the first stage of each channel where a pseudorandom sequence is injected before one of the channels. The difference between the digital outputs of two channels is used to drive an interpolation filter to correct the mentioned errors. Since splines modeled high nonlinearity with weakly nonlinear functions, it selected for interpolation filtering which results in low computational overhead and fast convergence time. Behavioral simulations of a 12-bit 100 MS/s pipelined ADC show that the convergence time of the algorithm is approximately 4 x 10(4) clock cycles and the signal-to-noise and distortion ratio and the spurious free dynamic range improved from 32 dB/35 dB to 70 dB/75 dB.