A fully digital Background calibration technique for pipeline analog-to-digital converters

摘要

This paper describes a new background calibration technique for pipeline analog-to-digital converters (ADCs). The new scheme utilizes an existing digital foreground calibration algorithm and extends it to work in background. The goal is to digitally calibrate the pipeline ADCs in the background without stopping the input conversion. In this method one additional stage connected in parallel to the stage under calibration and one cyclic ADC are used to accommodate the calibration. The extra stage and the cyclic ADC are only used during the calibration process. Sources of error in pipeline architectures and effects of error on residue plot of 1-bit per stage are identified and discussed. The digital background calibration accounts for capacitor mismatch, comparator offset, charge injection and finite op-amp gain. By applying proposed calibration to a 12 bit resolution pipeline ADC, maximum INL improved from 14 to 0.6 LSB, and maximum DNL improved from 26 to 0.8 LSB.