Design and Characterization of STI Compatible High-Voltage NMOS and PMOS Devices in Standard CMOS Process

摘要

This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25um/5V CMOS process technology. Breakdown voltages of 35V for n-channel with a specific on resistance of 1.96mΩ.cm~2 and -45V for p-channel with a specific on-resistance of 8.73mΩ.cm~2 have been achieved without any modification of existing standard CMOS process.