Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits

摘要

Processing techniques for 4H-SiC devices and circuits are optimized. The SiC mesa etching process has a variation of <;5% over the wafer. The average n-type contact resistivity is 1.15x10^-6 Ohm.cm². The fabricated devices and circuits with one-layer metal interconnect have high yield with no need of chemical-mechanical planarization process. More complex circuits with two-layer metal interconnect achieve high yield by applying chemical-mechanical planarization process.