Analysis of Interface Trap Density between Semiconductor- Gate insulator with C-V characteristics

机译：具有C-V特性的半导体栅绝缘子之间的界面陷阱密度分析

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In this paper, we analyzed interface trap density between pentacene and PVP and SiO2 gate dielectric by using high-low C-V characteristics. The interface trap density was 10~(13) cm~(-2)eV~(-1).

机译：在本文中，我们利用高-低C-V特性分析了并五苯与PVP和SiO2栅介质之间的界面陷阱密度。界面陷阱密度为10〜（13）cm〜（-2）eV〜（-1）。

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来源
《IMID/IDMC/ASIA DISPLAY 2008;International display manufacturing conference 2008;International meeting on information display;Asia display 2008》|2008年|p.645-647|共3页
会议地点 Ilsan(KR);Ilsan(KR);Ilsan(KR);Ilsan(KR)
作者
Seung-Hyeon Jeong; Se-Min Kim; Chung-Kun Song;
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作者单位

Dept. of Electronics engineering, Dong-A University, 840, Hadan-dong, Saha-Gu, Busan, Korea;

rnDept. of Electronics engineering, Dong-A University, 840, Hadan-dong, Saha-Gu, Busan, Korea;

rnDept. of Electronics engineering, Dong-A University, 840, Hadan-dong, Saha-Gu, Busan, Korea TEL:82-51-200-7711, e-mail: cksong@dau.ac.kr;

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原文格式 PDF
正文语种 eng
中图分类显示技术;显示设备、显示器;
关键词
interface trap density; pentacene; C-V characteristics;

机译：界面陷阱密度；并五苯; C-V特性;

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3. Density of Traps at the Insulator/III-N Interface of GaN Heterostructure Field-Effect Transistors Obtained by Gated Hall Measurements [J] . Mehari Shlomo, Gavrilov Arkady, Eizenberg Moshe, Electron Device Letters, IEEE . 2015,第9期

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8. Defect-Related Dielectric Breakdown, Change Trapping, and Interface-State Generation of Gate Oxides Grown on Zone-Melting-Recrystallized Silicon-on-Insulator Films [R] . Lee, C. T., Chen, C. K. 1989

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Analysis of Interface Trap Density between Semiconductor- Gate insulator with C-V characteristics

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