Method of forming PN junctions including a post-ion implant dynamic surface anneal process with minimum interface trap density at the gate insulator-silicon interface

摘要

A method of forming transistors on a wafer includes forming gates over gate insulators on a surface of the wafer and ion implanting dopant impurity atoms into the wafer to form source and drain regions aligned on opposite sides of each gate. The wafer is then annealed by pre-heating the bulk of the wafer to an elevated temperature over 350 degrees C. but below a temperature at which the dopant atoms tend to cluster. Meanwhile, an intense line beam is produced having a narrow dimension along a fast axis from an array of coherent CW lasers of a selected wavelength. This line beam is scanned across the surface of the heated wafer along the direction of the fast axis, so as to heat, up to a peak surface temperature near a melting temperature of the wafer, a moving localized region on the surface of the wafer having (a) a width corresponding to the narrow beam width and (b) an extremely shallow below-surface depth. During the scanning step, the surface state density at the interface between the semiconductor material and the gate insulator is minimized by continuing to maintain the temperature of the bulk of the wafer outside of the moving localized region at said elevated temperature, while maintaining the rate at which the line beam is scanned along the fast axis at a rate in excess of 300 mm/sec.