PA-ZSA (Power-A ware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI

摘要

This paper describes a slack budget distribution algorithm for ultra-low power CMOS logic circuits in a VLSI design environment. We introduce Power-Aware Zero-Slack Algorithm (PA-ZSA), which distributes the surplus time slacks into the most power-hungry modules. The PA-ZSA ensures that the total slack budget is near-maximal and the total power is minimal as a power-aware version of the well-known zero-slack algorithm (ZSA). Based on these time slacks, we have conducted the low-power optimization at gate level by using technology scaling technique. The experimental results show that our strategy reduces average 36% of the total (static and dynamic) power over the conventional slack budget distribution algorithms.