Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities

摘要

A unique, efficient method and system for reliability simulation of a semiconductor chip design comprising millions of transistors. Specifically, the instant method starts by storing device information about a chip design as inputted. Next, by first partitioning the complex circuit of the design into numerous smaller stages, each of which confines direct current flow within its boundary, then estimating the current consumption and the relative current contribution of each transistor for each stage, the method of the present invention determines the individual currents of all power network transistors with sufficient accuracy for reliability simulation. The instant method then uses the individual transistor currents and the stored device information, including data of an accurate resistor-capacitor model of the power network, to determine the branch currents and node voltages in all interconnect wires of the power network. Finally, the instant method reports all potential problems of the design identified based on the values of the branch currents and node voltages. As such, the present invention enables circuit designers to pinpoint where voltage drop and electro-migration may pose problems and take appropriate corrective actions before chips are fabricated and sold. Thus, the present invention provides a novel and superior method for reliability simulation over the prior art by offering much greater simulation speed and capacity over conventional reliability simulation tools while delivering highly accurate results for reliability analysis crucial to today's deep sub-micron CMOS designs.