首页> 外文期刊>Device and Materials Reliability, IEEE Transactions on >Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design
【24h】

Ultra-Low Power, Highly Reliable, and Nonvolatile Hybrid MTJ/CMOS Based Full-Adder for Future VLSI Design

机译:基于超低功耗,高可靠性和非易失性的混合MTJ / CMOS混合全加器,用于未来的VLSI设计

获取原文
获取原文并翻译 | 示例

摘要

Very large-scale integrated circuit design, based on today’s CMOS technologies, are facing various challenges. Shrinking transistor dimensions, reduction in threshold voltage, and lowering power supply voltage, cause new concerns such as high leakage current, and increase in radiation sensitivity. As a solution for such design challenges, hybrid MTJ/CMOS based design can resolve the issue of leakage power and bring the advantage of nonvolatility. However, radiation-induced soft error is still an issue in such new designs as they need peripheral CMOS components. As a result, these magnetic-based circuits are still susceptive to radiation effects. This paper proposes a radiation hardened and low power magnetic full-adder (MFA) for advanced microprocessors. Comparing with the previous work, the proposed MFA is capable of tolerating any particle strike regardless of the induced charge. Besides, our MFA circuit offers a lower energy consumption in write operation as compared with previous counterparts. We also suggest an incremental modification to the proposed MFA circuit to give it the advantage of full nonvolatility for future nonvolatile microprocessors.
机译:基于当今的CMOS技术的超大规模集成电路设计正面临各种挑战。晶体管尺寸的缩小,阈值电压的降低以及电源电压的降低,引起了新的担忧,例如高泄漏电流和辐射敏感性的提高。作为针对此类设计挑战的解决方案,基于MTJ / CMOS的混合设计可以解决漏电问题,并带来非易失性的优势。但是,辐射诱导的软错误在此类新设计中仍然是一个问题,因为它们需要外围CMOS组件。结果,这些基于磁性的电路仍然容易受到辐射影响。本文提出了一种用于高级微处理器的辐射硬化和低功率磁性全加器(MFA)。与以前的工作相比,拟议的MFA能够容忍任何粒子撞击,无论感应电荷如何。此外,与之前的同类产品相比,我们的MFA电路在写入操作中具有更低的能耗。我们还建议对建议的MFA电路进行增量修改,以使其具有未来非易失性微处理器完全非易失性的优势。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号