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Charge trapping non-volatile memory device and method of fabricating the same and method of operating the charge trapping non-volatile memory device

机译:电荷捕获非易失性存储器件和制造相同的方法和操作电荷捕获非易失性存储器件的方法

摘要

The charge trap nonvolatile memory device includes a source region and a drain region spaced apart from each other by a first trapping region, a channel region, and a second trapping region in an upper region of a substrate, and a gate disposed on the substrate in the channel region. a stack, a first tunnel insulating layer, a first charge trapping layer, and a first blocking insulating layer disposed over the substrate in the first trapping region; a second tunnel insulating layer disposed over the substrate in the second trapping region; 2 The charge trap layer and the second blocking insulating layer, the interlayer insulating layer disposed on the substrate to cover the gate stack, and the first and second contacts passing through the interlayer insulating layer to contact the source region and the drain region, respectively The plug and a third contact plug passing through the interlayer insulating layer to contact the upper surface of the gate stack and overlap the first charge trap layer of the first trapping region and the second charge trap layer of the second charge trapping region includes
机译:电荷陷阱非易失性存储器件包括源区和通过第一捕获区域,沟道区和第二捕获区域彼此间隔开的漏极区域,并且在基板的上部区域中,以及设置在基板上的栅极沟道区。堆叠,第一隧道绝缘层,第一电荷俘获层和设置在第一捕获区域中的基板上的第一阻挡绝缘层;在第二捕获区域中设置在基板上的第二隧道绝缘层; 2电荷捕集层和第二阻挡绝缘层,设置在基板上的层间绝缘层以覆盖栅极堆叠,以及通过层间绝缘层的第一和第二触点分别接触源区和漏极区域。插头和通过层间绝缘层的第三接触插头与栅极堆叠的上表面接触并重叠第一捕获区域的第一电荷阱层,第二电荷俘获区域的第二电荷阱层包括

著录项

  • 公开/公告号KR102300122B1

    专利类型

  • 公开/公告日2021-09-09

    原文格式PDF

  • 申请/专利权人 에스케이하이닉스 주식회사;

    申请/专利号KR20150024489

  • 发明设计人 권영준;

    申请日2015-02-17

  • 分类号H01L27/115;

  • 国家 KR

  • 入库时间 2022-08-24 20:58:11

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