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INTEGRATED CIRCUIT COMPRISING DEPLETED SOI-TYPE SEMICONDUCTOR DEVICE

机译:包含耗尽型SOI半导体器件的集成电路

摘要

PROBLEM TO BE SOLVED: To provide an integrated circuit comprising a delay circuit, where basically comprising a depleted SOI-type semiconductor device, the design layout (design property) for a conventional bulk MOS semiconductor device is diverted with no significant modification, while stable operation is assured with no slow down of operation as the entire circuit. ;SOLUTION: This integrated circuit comprises first circuits 11, 12, and 13 comprising a first depleted SOI-type semiconductor device, and a second circuit 14 which comprises a second depleted SOI-type semiconductor device and causes time delays. Here, the first depletion SOI type semiconductor device comprises a body float type depleted SOI-type semiconductor device, while the second depletion SOI type semiconductor device comprises a body tied type depleted SOI-type semiconductor device.;COPYRIGHT: (C)2001,JPO
机译:要解决的问题:为了提供一种包括延迟电路的集成电路,其中基本上包括耗尽的SOI型半导体器件,传统的体MOS半导体器件的设计布局(设计特性)在没有明显改变的情况下被转移,同时稳定运行确保整个电路的运行不会减慢。解决方案:该集成电路包括:第一电路11、12和13,其包括第一耗尽型SOI型半导体器件;第二电路14,其包括第二耗尽型SOI型半导体器件,并引起时间延迟。在此,第一耗尽型SOI型半导体器件包括体浮型耗尽型SOI型半导体器件,而第二耗尽型SOI型半导体器件包括体束缚型耗尽型SOI型半导体器件。版权所有:(C)2001,JPO

著录项

  • 公开/公告号JP2001044440A

    专利类型

  • 公开/公告日2001-02-16

    原文格式PDF

  • 申请/专利权人 SONY CORP;

    申请/专利号JP19990215477

  • 发明设计人 NAKAYAMA SO;

    申请日1999-07-29

  • 分类号H01L29/786;H01L27/12;

  • 国家 JP

  • 入库时间 2022-08-22 01:29:05

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