首页> 外国专利> The semiconductor integrated circuit analysis device, a semiconductor integrated circuit analysis method and a semiconductor integrated circuit recording medium storing a program for executing the analysis method

The semiconductor integrated circuit analysis device, a semiconductor integrated circuit analysis method and a semiconductor integrated circuit recording medium storing a program for executing the analysis method

机译:半导体集成电路分析装置,半导体集成电路分析方法以及存储用于执行该分析方法的程序的半导体集成电路记录介质

摘要

A semiconductor device analyzer has a substrate model reading module, a Y-matrix entry module, a discriminating module, a matrix reduction module, and an output format discriminating module. The substrate model reading module reads a substrate network model of three-dimensional meshes representing the substrate of a semiconductor device. The substrate network model is a network of resistive and capacitive elements and is used for the simulation and analysis of the semiconductor substrate. The Y-matrix entry module prepares a Y-matrix from the substrate network model, each element of the Y-matrix being expressed with a polynomial of differential operator "s". The discriminating module discriminates internal nodes to be eliminated from external nodes to be left among the nodes of the substrate network model. The matrix reduction module eliminates the internal nodes, thereby reducing the Y-matrix. The output format determining module determines an output format for an operation result.
机译:半导体器件分析仪具有衬底模型读取模块,Y矩阵输入模块,判别模块,矩阵约简模块和输出格式判别模块。衬底模型读取模块读取代表半导体器件的衬底的三维网格的衬底网络模型。衬底网络模型是电阻性和电容性元素的网络,用于半导体衬底的仿真和分析。 Y矩阵输入模块从衬底网络模型准备一个Y矩阵,Y矩阵的每个元素都用微分算子“ s”的多项式表示。区分模块从基板网络模型的节点之中将要去除的内部节点与剩余的外部节点进行区分。矩阵缩减模块消除了内部节点,从而缩减了Y矩阵。输出格式确定模块确定操作结果的输出格式。

著录项

  • 公开/公告号JP3670553B2

    专利类型

  • 公开/公告日2005-07-13

    原文格式PDF

  • 申请/专利权人 株式会社東芝;

    申请/专利号JP20000087643

  • 发明设计人 木村 智寿;奥村 万規子;

    申请日2000-03-27

  • 分类号G01R31/316;G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 22:29:11

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