首页> 外国专利> SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY REPAIR METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTER READABLE RECORDING MEDIUM STORED WITH PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE METHOD

SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY REPAIR METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND COMPUTER READABLE RECORDING MEDIUM STORED WITH PROGRAM FOR ALLOWING COMPUTER TO EXECUTE THE METHOD

机译:半导体集成电路,用于半导体集成电路的存储器修复方法以及存储有程序的计算机可读记录介质以允许计算机执行该方法

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for improving yield.;SOLUTION: This semiconductor integrated circuit is provided with plural RAM 10-12, a supplementary RAM 13, test/repair control logics 2 and 3 for testing the failure detection of the plural RAM 10-12, and selectors 20-23 and 30-32 for supplying the supplementary RAM 13 corresponding to the RAM whose failure is detected among the plural RAM 10-12 based on a repair control signal corresponding to the test results obtained by the test/repair control logics 2 and 3.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种用于提高成品率的半导体集成电路;解决方案:该半导体集成电路配备有多个RAM 10-12,一个辅助RAM 13,测试/维修控制逻辑2和3,用于测试故障的检测。多个RAM 10-12,以及选择器20-23和30-32,用于根据与通过测试获得的测试结果相对应的修复控制信号,提供与多个RAM 10-12之中检测到故障的RAM相对应的补充RAM 13。测试/维修控制逻辑2和3 .;版权:(C)2002,JPO

著录项

  • 公开/公告号JP2002014875A

    专利类型

  • 公开/公告日2002-01-18

    原文格式PDF

  • 申请/专利权人 MITSUBISHI ELECTRIC CORP;

    申请/专利号JP20000199859

  • 发明设计人 YAMAMOTO SEIJI;GOTO KOJI;OKAMOTO YASUSHI;

    申请日2000-06-30

  • 分类号G06F12/16;G01R31/28;G11C29/00;

  • 国家 JP

  • 入库时间 2022-08-22 01:00:15

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