A memory cell array structure of a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory device, the memory cell array access method of the apparatus, NAND flash memory device and semiconductor memory

摘要

A non-volatile memory device has a main-memory cell array, and a sub-memory cell array, the latter consisting of a number of NAND-cell rows each consisting of a number of memory cell transistors where the number of memory cell transistors in the cell rows is less than the number of memory cell transistors in the NAND-rows of the main memory cell array. During programming and erasure, the sub-memory cell array is operatively joined to the main bit lines of the main-memory cell array, and has separate read-path independent of the that of the main-memory cell array. Independent claims are given for the following. (1) Memory cell array structure; (2) Electrically programmable non-volatile semiconductor memory device; (3) Method for accessing memory cell array; (4) NAND-flash memory device.