A processor (10) of processes data using a cache circuit (12). The processor (20) is coupled to a functionally detachable device (19) via the cache circuit (12). When a cache line is loaded into cache memory (120), it is tested whether the cache line has an address within a detachable device address range allocated to the detachable device (19). If so, identification of the cache line, or a range of addresses that includes the address of the cache line is stored. When a flush command is received that requires write back cached data to the detachable device, the identification is used to select the cache line for selective write back to the detachable device. Thus less cache data needs to be invalidated when a device is functionally detached from the circuit.
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