首页> 外国专利> Performance in pfet - transistors with a metal gate stack with a large ε by improving of the dopant one chlusses

Performance in pfet - transistors with a metal gate stack with a large ε by improving of the dopant one chlusses

机译:通过改善一类掺杂剂在具有大ε的金属栅堆叠的pfet晶体管中的性能。

摘要

In a p - channel transistor with a metal gate electrodes structure with a large ε is a better dopant profile at least in the threshold value setting ends of semiconductor material, for example a silicon / germanium - material, achieved by a diffusion blocking locations, for example fluorine in front of the production of the threshold value setting ends of semiconductor material is installed. Consequently, the drain - and source expansion regions with a high dopant concentration are provided, such as this to generate the desired miller - capacity is required, without an undesirable dopant diffusion below the threshold value setting end semiconductor material is caused, which otherwise could result in increased leakage currents and a greater risk of breakdowns would lead.
机译:在具有大的ε的金属栅电极结构的p-沟道晶体管中,至少在例如通过扩散阻挡位置实现的半导体材料例如硅/锗材料的阈值设定端中,掺杂剂分布更好。在产生氟的阈值的前面设置半导体材料的设定端。因此,提供了具有高掺杂剂浓度的漏极-和源极扩展区,例如这样,以产生期望的密勒-容量,而不会引起低于阈值设定端的半导体材料的不希望的掺杂剂扩散,否则这可能导致泄漏电流增加会导致更大的击穿风险。

著录项

  • 公开/公告号DE102009047304A1

    专利类型

  • 公开/公告日2011-06-01

    原文格式PDF

  • 申请/专利权人

    申请/专利号DE20091047304

  • 发明设计人

    申请日2009-11-30

  • 分类号H01L21/336;H01L21/22;H01L21/8238;H01L29/78;

  • 国家 DE

  • 入库时间 2022-08-21 17:47:39

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