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SEMICONDUCTOR LAYOUT SETTING DEVICE, SEMICONDUCTOR LAYOUT SETTING METHOD, AND SEMICONDUCTOR LAYOUT SETTING PROGRAM

机译:半导体布局设置设备,半导体布局设置方法和半导体布局设置程序

摘要

PROBLEM TO BE SOLVED: To properly insert a repeater buffer while avoiding chip area increase.SOLUTION: A semiconductor device of a layout target includes: first and second power source domains; and wiring for connecting a connection source and a connection destination belonging to the second power source domain. A wiring inhibition and permission region setting section 120 sets an exclusive wiring inhibition region and a passing wiring permission region in the first power source domain on the basis of a repeater wiring maximum length which is a maximum wiring length with which a repeater buffer can drive. A wiring setting section 130 corrects the wiring on the basis of the exclusive wiring inhibition region and the passing wiring permission region. A repeater insertion section 140 sets the repeater buffer inserted into the wiring according to the repeater wiring maximum length. The exclusive wiring inhibition region permits the wiring connected in the first power source domain and inhibits passing wiring. The passing wiring permission region is a region in which the exclusive wiring inhibition region is excluded from the first power source domain and permits the passing wiring.
机译:解决的问题:在避免芯片面积增加的同时正确地插入转发器缓冲器。解决方案:布局目标的半导体器件包括:第一和第二电源域;用于连接属于第二电源域的连接源和连接目的地的配线。布线禁止和允许区域设置部分120基于作为中继器缓冲器可驱动的最大布线长度的转发器布线最大长度,在第一电源域中设置排他布线禁止区域和通过布线允许区域。配线设定部130基于排他配线禁止区域和通过配线允许区域来校正配线。中继器插入部分140根据中继器布线最大长度来设置插入到布线中的中继器缓冲器。排他配线禁止区域允许在第一电源域中连接的配线并且禁止通过配线。通过布线允许区域是其中排他布线禁止区域从第一电源域中排除并且允许通过布线的区域。

著录项

  • 公开/公告号JP2013045861A

    专利类型

  • 公开/公告日2013-03-04

    原文格式PDF

  • 申请/专利权人 RENESAS ELECTRONICS CORP;

    申请/专利号JP20110182200

  • 发明设计人 FUTAKATA HIDEAKI;

    申请日2011-08-24

  • 分类号H01L21/82;H01L21/822;H01L27/04;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 16:57:47

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