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Semiconductor device having an NMOS transistor and a PMOS transistor including a buried Si / Ge material to produce a tensile strain and compressive strain

机译:具有NMOS晶体管和PMOS晶体管的半导体器件,其包括掩埋的Si / Ge材料以产生拉伸应变和压缩应变

摘要

While (105A, 205A, 305A, 405A) in the active region of the one, to form a semiconductor alloy uniform and substantially continuously (107,207,307,407), (105B, 205B second active region, In order to provide (113B, 213B, and 313B, 401) semiconductor material for the base in the central portion 305B, the 405B), by patterning semiconductor alloy (107,207,307,407) there is distortion of the heterogeneous can be induced. On the other hand, after providing the cover layer corresponding (113A, 213A, 313A, 413A) in the semiconductor material of the base, established process techniques for forming the gate dielectric (122,322,422) is used Ur. In some example embodiments, a self-aligned process substantially is provided. In this process, the gate electrodes (121,221,321,421) is formed on the basis of the layer (208, 308), said layer (208, 308), one (205B, 305B) of the active region it can also be used to define (213B, 313B) and the central portion of the semiconductor material of the base. Therefore, by using semiconductor alloy single (107,207,307,407), performance (120A, 120B) of the transistors of different conductivity types can be improved independently.
机译:(105A,205A,305A,405A)在一个有源区中,形成均匀且基本连续的半导体合金(107,207,307,407),(105B,205B第二有源区,为了提供(113B,213B,和313B) 401)在中心部分305B,405B)中作为基底的半导体材料,通过图案化半导体合金(107,207,307,407),可以引起异质变形。另一方面,在基底的半导体材料中设置对应的覆盖层(113A,213A,313A,413A)之后,使用已形成的用于形成栅极电介质(122,322,422)的工艺技术。在一些示例实施例中,基本上提供了自对准过程。在此过程中,栅电极(121,221,321,421)是基于层(208,308)形成的,所述层(208,308),有源区之一(205B,305B)也可以用来定义( 213B,313B)和基底的半导体材料的中心部分。因此,通过使用单一的半导体合金(107,207,307,407),可以独立地提高不同导电类型的晶体管的性能(120A,120B)。

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