首页> 外国专利> Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same

Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same

机译:半导体装置,包括位线接触插头和掩埋沟道阵列晶体管,以及半导体模块,电子电路板和包括该半导体系统的电子系统

摘要

A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
机译:具有单元区域和外围区域的半导体器件包括:半导体衬底;在单元区域中限定半导体衬底的单元有源区域的单元绝缘隔离区域;在单元区域中布置在半导体衬底内的字线;位设置在单元有源区上的线接触塞,设置在位线接触塞上的位线,在外围区域中界定半导体衬底的外围有源区域的外围绝缘隔离区以及包括外围晶体管下电极的外围晶体管外围晶体管上电极。位线接触插塞在半导体器件中形成为与外围晶体管下电极相同的高度,并且位线电极在半导体器件中形成为与外围晶体管下电极相同的高度。

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