首页> 外国专利> Semiconductor Device Including a Bit Line Contact Plug and a Buried Channel Array Transistor and Method of Fabricating the Same and a Semiconductor Module an Electronic Circuit Board and an Electronic System including the Same

Semiconductor Device Including a Bit Line Contact Plug and a Buried Channel Array Transistor and Method of Fabricating the Same and a Semiconductor Module an Electronic Circuit Board and an Electronic System including the Same

机译:包括位线接触塞和埋入式沟道阵列晶体管的半导体器件及其制造方法和半导体模块,电路板和包括该电路板的电子系统

摘要

Semiconductor devices including a bit line contact plug and a buried channel array transistor, a method of manufacturing the semiconductor device, and a semiconductor module, an electronic circuit board, and an electronic system including the semiconductor device are introduced. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: preparing a semiconductor substrate including a cell region and a peripheral region; forming a cell insulating isolation region defining a cell active region in the semiconductor substrate corresponding to the cell region; A word line crossing the cell active region and the cell isolation region in a semiconductor substrate corresponding to the cell region and forming a bit line contact plug electrically connected to the cell active region on the cell active region Forming a bit line electrically connected to the bit line contact plug on the bit line contact plug and forming a peripheral insulating isolation region defining a peripheral active region in the semiconductor substrate corresponding to the peripheral region, On the semiconductor substrate corresponding to the peripheral active region, Wherein the bit line contact plug is formed at the same level as the peripheral transistor lower electrode, and the bit line is formed at the same level as the peripheral transistor upper electrode .
机译:介绍了包括位线接触塞和掩埋沟道阵列晶体管的半导体器件,该半导体器件的制造方法以及包括该半导体器件的半导体模块,电子电路板和电子系统。根据本发明的一个方面,提供了一种制造半导体器件的方法,包括:制备包括单元区域和外围区域的半导体衬底;在半导体衬底中形成与单元区域相对应的单元绝缘隔离区域,该单元绝缘隔离区域限定单元有源区域;字线穿过与单元区域相对应的半导体衬底中的单元有源区域和单元隔离区域,并形成位线接触插塞,该位线接触插塞电连接至单元有源区域上的单元有源区域,从而形成与位电连接的位线线接触插塞在位线接触插塞上并形成外围绝缘隔离区,该外围绝缘隔离区在对应于外围区域的半导体衬底中限定出外围有源区域,在与外围有源区域相对应的半导体衬底上,形成位线接触插塞位线形成在与外围晶体管下电极相同的水平,并且位线形成在与外围晶体管下电极相同的水平。

著录项

  • 公开/公告号KR101718980B1

    专利类型

  • 公开/公告日2017-03-23

    原文格式PDF

  • 申请/专利权人 삼성전자주식회사;

    申请/专利号KR20100031564

  • 发明设计人 김봉수;조관식;

    申请日2010-04-06

  • 分类号H01L21/8242;H01L27/108;

  • 国家 KR

  • 入库时间 2022-08-21 13:25:50

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