首页> 外国专利> PACKAGE SUBSTRATE AND A MANUFACTURING METHOD THEREOF CAPABLE OF IMPROVING THE CONNECTION RELIABILITY OF A SOLDER BUMP

PACKAGE SUBSTRATE AND A MANUFACTURING METHOD THEREOF CAPABLE OF IMPROVING THE CONNECTION RELIABILITY OF A SOLDER BUMP

机译:能够提高焊锡连接的连接可靠性的封装基板及其制造方法

摘要

PURPOSE: A package substrate and a manufacturing method thereof are provided to reduce the manufacturing costs and time by removing a copper plating process on the upper and lower sides of a base substrate and the inner side of a via hole.;CONSTITUTION: A circuit pattern(110) is formed on the upper side of a base substrate(100). The base substrate is composed of a copper laminate plate. A plurality of via holes(121) are formed on the base substrate for interlayer conduction. The via is formed by filling the inner side of the via hole with conductive paste without a copper plating process. A solder bump(200) surrounds a protrusive part(122) of the via. A solder resist layer(130) is formed on the upper and lower sides of the base substrate to protect the circuit pattern.;COPYRIGHT KIPO 2013
机译:目的:提供一种封装基板及其制造方法,以通过去除基础基板的上,下侧和通孔的内侧上的镀铜工艺来减少制造成本和时间。组成:电路图案(110)形成在基础基板(100)的上侧。基础基板由铜层压板组成。多个通孔(121)形成在基础基板上用于层间导电。通过在不进行镀铜处理的情况下用导电膏填充通孔的内侧来形成通孔。焊料凸块(200)围绕通孔的突出部分(122)。在基础基板的上,下表面分别形成阻焊层(130),以保护电路图案。; COPYRIGHT KIPO 2013

著录项

  • 公开/公告号KR20130033160A

    专利类型

  • 公开/公告日2013-04-03

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRO-MECHANICS CO. LTD.;

    申请/专利号KR20110097066

  • 发明设计人 MOK JEE SOO;

    申请日2011-09-26

  • 分类号H01L23/48;H01L23/12;H01L21/60;

  • 国家 KR

  • 入库时间 2022-08-21 16:27:27

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