首页> 外国专利> INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SALICIDE CONTACTS ON NON-PLANAR SOURCE/DRAIN REGIONS

INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH SALICIDE CONTACTS ON NON-PLANAR SOURCE/DRAIN REGIONS

机译:用于在非平面源/漏区上形成带有硅化物接触的集成电路的集成电路和方法

摘要

Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a fin over a semiconductor substrate. The method further includes selectively epitaxially growing a silicon-containing material on the fin and providing the fin with a diamond-shaped cross-section and with an upper portion and a lower portion. The lower portion of the fin is covered with a masking layer. Further, a salicide layer is formed on the upper portion of the fin, and the masking layer prevents formation of the salicide layer on the lower portion of the fin.
机译:提供了集成电路和用于制造集成电路的方法。在一个实施例中,一种用于制造集成电路的方法包括在半导体衬底上方形成鳍。该方法还包括在鳍片上选择性地外延生长含硅材料,并为鳍片提供菱形横截面并且具有上部和下部。鳍片的下部覆盖有掩模层。此外,在鳍片的上部形成自对准硅化物层,并且掩模层防止在鳍片的下部形成自对准硅化物层。

著录项

  • 公开/公告号US2014131777A1

    专利类型

  • 公开/公告日2014-05-15

    原文格式PDF

  • 申请/专利权人 GLOBALFOUNDRIES INC.;

    申请/专利号US201213677651

  • 发明设计人 HOONG SHING WONG;MIN-HWA CHI;

    申请日2012-11-15

  • 分类号H01L29/78;H01L21/04;

  • 国家 US

  • 入库时间 2022-08-21 16:09:42

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号