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Integrated circuit devices having buried interconnect structures therein that increase interconnect density

机译:在其中具有增加互连密度的掩埋互连结构的集成电路器件

摘要

Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer. A second electrical interconnect is also provided, which extends on: (i) an upper surface of the first trench isolation region, (ii) the electrically insulating capping pattern; and (iii) the sidewall of the recess. The first and second electrical interconnects extend across the semiconductor substrate in first and second orthogonal directions, respectively.
机译:集成电路器件包括其中具有多个沟槽隔离区域的半导体衬底,该沟槽隔离区域在它们之间限定了相应的半导体有源区域。在半导体衬底中提供沟槽。沟槽具有第一和第二相对侧壁,第一和第二相对侧壁分别限定了与第一沟槽隔离区域和第一有源区域的相对界面。在沟槽的底部提供第一电互连。提供了电绝缘的覆盖图案,其在第一电互连和沟槽的顶部之间延伸。还提供了互连绝缘层,其互连沟槽的第一侧壁和第二侧壁以及底部。互连绝缘层在第一电互连和第一有源区之间延伸。在第一有源区域中提供凹槽。凹槽具有限定与互连绝缘层的界面的侧壁。还提供了第二电互连,该第二电互连在:(i)第一沟槽隔离区的上表面;(ii)电绝缘盖图案;以及(iii)凹槽的侧壁。第一和第二电互连分别在第一和第二正交方向上跨过半导体衬底延伸。

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