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Multilevel interconnect structure for high density integrated circuit devices, integrated circuit memories

机译:用于高密度集成电路器件的多层互连结构,集成电路存储器

摘要

A multilevel interconnect is formed which uses air (74) as a dielectric between wiring lines (66) bounded on an upper surface by a capping layer (70). A sacrificial layer is used to separate the wiring lines and is consumed leaving air gaps. A multilevel interconnect is formed which uses air as a dielectric between wiring lines. A pattern of wiring lines is formed over an insulating layer (62), a first wiring line is laterally separated from a second wiring line by a sacrificial layer. The surface of this layer is recessed below the surfaces of the wiring lines. A capping layer (70) is formed over the recessed surface and the wiring lines. The sacrificial layer is consumed through the capping layer leaving an air dielectric (74) between the two wiring lines bounded on an upper surface by the capping layer.
机译:形成多层互连,该多层互连使用空气(74)作为由覆盖层(70)限定在上表面上的布线(66)之间的电介质。牺牲层用于分隔布线,并且被消耗掉而留下气隙。形成使用空气作为布线之间的电介质的多层互连。在绝缘层(62)上形成布线的图案,第一布线通过牺牲层与第二布线横向分离。该层的表面在布线的表面下方凹陷。在凹陷表面和布线上方形成覆盖层(70)。牺牲层通过覆盖层被消耗,从而在由覆盖层限定在上表面上的两条布线之间留下空气电介质(74)。

著录项

  • 公开/公告号DE19747559A1

    专利类型

  • 公开/公告日1999-05-06

    原文格式PDF

  • 申请/专利权人 UNITED MICROELECTRONICS CORP. HSINCHU TW;

    申请/专利号DE1997147559

  • 发明设计人 SUN SHIH-WEI TAIPEI TW;

    申请日1997-10-28

  • 分类号H01L21/768;H01L23/522;

  • 国家 DE

  • 入库时间 2022-08-22 02:13:07

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