Power bus integrity is a continuing challenge for high performance designs in deep submicron technologies. Leading edge products with hundreds of million transistors, gigahertz clock speeds, supply voltages as low as 500-700 millivolts and supply currents of more than a hundred amps are planned at the 45nm process node [1]. Product architecture, circuit design techniques, and process optimizations can all be used to minimize switching transients however effective supply bypass capacitance is still mandatory since power bus transients ultimately degrade product performance. Most decoupling "bypass" capacitors are usually found in the form of discrete surface mountable (SMT) components with 2 leads which values range from picofarads to tens of microfarads. The most frequent technology for discrete capacitors is that of the socalled Multi-Layer Ceramic Capacitors, or MLCC. Surface Mountable MLCC devices have normalized sizes (Fig.1).
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