首页> 外国专利> Method for manufacturing contact holes in CMOS device using gate-last process

Method for manufacturing contact holes in CMOS device using gate-last process

机译:利用后栅极工艺在CMOS器件中制造接触孔的方法

摘要

The present invention provides a method for manufacturing contact holes in a CMOS device by using a gate-last process, comprising: forming high-K dielectrics/metal gates (HKMG) of a first type MOS; forming and metalizing lower contact holes of the source/drain of a first type MOS and a second type MOS as well as forming HKMG of a second type MOS simultaneously, wherein the lower contact holes of the source/drain are filled with the same material as that used by the metal gate of the second type MOS; forming and metalizing contact holes of metal gates of a first type MOS and a second type MOS as well as upper contact holes of the source/drain, wherein the upper contact holes of the source/drain are aligned with the lower contact holes of the source/drain. The method reduces the difficulty of contact hole etching and metal deposition, simplifies the process steps, and increases the reliability of the device.
机译:本发明提供一种通过使用后栅极工艺在CMOS器件中制造接触孔的方法,包括:形成第一类型MOS的高K电介质/金属栅极(HKMG);形成并金属化第一类型MOS和第二类型MOS的源极/漏极的下部接触孔,以及同时形成第二类型MOS的HKMG,其中,源极/漏极的下部接触孔填充有与第二类MOS的金属栅极所使用的金属;形成并金属化第一类型MOS和第二类型MOS的金属栅极的接触孔以及源极/漏极的上接触孔,其中源极/漏极的上接触孔与源极的下接触孔对准/排水。该方法降低了接触孔蚀刻和金属沉积的难度,简化了工艺步骤,并增加了器件的可靠性。

著录项

  • 公开/公告号US8759208B2

    专利类型

  • 公开/公告日2014-06-24

    原文格式PDF

  • 申请/专利权人 JIANG YAN;

    申请/专利号US201113141982

  • 发明设计人 JIANG YAN;

    申请日2011-02-21

  • 分类号H01L21/3205;

  • 国家 US

  • 入库时间 2022-08-21 16:03:34

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号