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VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY
VERTICAL III-V NANOWIRE FIELD-EFFECT TRANSISTOR USING NANOSPHERE LITHOGRAPHY
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机译:纳米球面光刻技术用于垂直III-V型纳米电子场效应晶体管
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摘要
A vertical III-V nanowire Field-Effect Transistor (FET). The FET includes multiple nanowires or nanopillars directly connected to a drain contact, where each of the nanopillars includes a channel of undoped III-V semiconductor material. The FET further includes a gate dielectric layer surrounding the plurality of nanopillars and a gate contact disposed on a gate metal which is connected to the gate dielectric layer. Additionally, the FET includes a substrate of doped III-V semiconductor material connected to the nanopillars via a layer of doped III-V semiconductor material. In addition, the FET contains a source contact directly connected to the bottom of the substrate. By having such a structure, electrostatic control and integration density is improved. Furthermore, by using III-V materials as opposed to silicon, the current drive capacity is improved. Additionally, the FET is fabricated using nanosphere lithography which is less costly than the conventional photo lithography process.
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