首页> 外国专利> Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor

Integrated electrostatic discharge (ESD) clamping for an LDMOS transistor device having a bipolar transistor

机译:具有双极型晶体管的LDMOS晶体管器件的集成静电放电(ESD)钳位

摘要

A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.
机译:一种制造具有用于静电放电(ESD)保护的双极晶体管的横向扩散的金属氧化物半导体(LDMOS)晶体管器件的方法,该方法包括掺杂衬底以在衬底中形成LDMOS晶体管器件的主体区,该主体区具有第一导电类型,在衬底中形成LDMOS晶体管器件的掺杂隔离区,该掺杂隔离区具有第二导电类型并围绕LDMOS晶体管器件的其中设置有主体区的器件区域,从而形成基极接触形成双极晶体管的区域,将基极接触区域设置在主体区域内并具有第一导电类型,并掺杂衬底以形成用于限定双极晶体管的集电极区域的掺杂隔离区域的隔离接触区域,以形成衬底中LDMOS晶体管器件的源极和漏极区,并形成双极晶体管的发射极区身体区域内的电阻器。

著录项

  • 公开/公告号US9673188B2

    专利类型

  • 公开/公告日2017-06-06

    原文格式PDF

  • 申请/专利权人 WEIZE CHEN;PATRICE M. PARRIS;

    申请/专利号US201514966688

  • 发明设计人 PATRICE M. PARRIS;WEIZE CHEN;

    申请日2015-12-11

  • 分类号H01L27/07;H01L27/02;H01L21/762;H01L29/78;H01L29/66;H01L21/768;H01L29/06;H01L29/10;

  • 国家 US

  • 入库时间 2022-08-21 13:42:02

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