MOS-transistor structure with pedestal for protection against electrostatic discharges, has ESD-protection device provided on MOS-transistor base and transistor configuration is generated with an ESD-protection transistor

摘要

Integrated circuit design demands that electrostatic discharge (ESD) occurrences should be blocked from the transistor gates, particular in the case of those transistors which operate as circuit buffers, and this fully applies even though integrated circuits and ESDP-devices are becoming smaller. An ESDP device is now provided on the MOS-transistor base and a transistor configuration is generated with an ESDP-transistor which eliminates the formation of the lightly doped drain (LDD) zone directly underneath the surface of the transistor in the source and drain zones. The transistor configuration is a MOS-transistor with an ESD-pedestal with the semiconductor material in the active zones adjacent to the gate etched (buried) to a given depth beneath the plane of the interface between the gate and its gate-oxide.