Aspects disclosed in the detailed description include memory controller placement in a three dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through silicon via (TSV) farms. In this regard in one aspect a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire length between the memory controller and each of the multiple TSV farms. In another aspect multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC latency of memory access requests is minimized.
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