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Design exploration for three-dimensional integrated circuits (3DICs).

机译:三维集成电路(3DIC)的设计探索。

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摘要

With technologies scaling, interconnect delay and power consumption has become dominant in deep submicron designs. Three-dimensional Integrated Circuits (3D ICs) have recently emerged as a promising means to mitigate these interconnect-related problems. By stacking multiple active device layers with vertical interconnect, 3D technologies offer designers great opportunities meeting performance and power requirements. Compared to traditional 2D design, 3D technologies provide shorter global interconnects, higher performance, less power consumption, higher packing density and smaller footprints, and low cost mixed-technology capabilities. However, 3D ICs pose several challenges before developing into viable commercial product. First, there is no commercial 3D Electrical Design Automation (EDA) tools to support 3D IC design. Second, there is a lack of testing and verification tools and methods to ensure the correct functionality of 3D ICs. Third, design space exploration at the architectural level is essential to take full advantage of 3D integration. Therefore, as fabrication of 3D architecture becomes feasible, it is urgent to develop corresponding 3D EDA tools and 3D testing methodologies for designers to explore 3D ICs design space and evaluate 3D benefits at architectural level.;This work is intended to address EDA, testing, and architectural exploration challenges faced by 3D ICs by exploring five areas. First, the electrical characteristics of Inter-tier Connections is analyzed for 3D ICs. This evaluation is essential for timing analysis and better system design for 3D IC. Second, a 3D ICs design flow based on OpenAccess (OA) platform is presented. Third, we address the scan chain ordering and optimization problem in 3D ICs. Fourth, Test Access Mechanism (TAM) optimization for core-based 3D System-on-chip (SOC) is discussed. Finally, hybrid cache architecture, which combines traditional SRAM and several emerging non-volatile memory technologies, is explored in 2D as well as 3D space.
机译:随着技术的扩展,互连延迟和功耗已成为深亚微米设计中的主要问题。三维集成电路(3D IC)最近作为缓解这些互连相关问题的有前途的手段而出现。通过将多个有源设备层与垂直互连堆叠在一起,3D技术为设计人员提供了满足性能和功耗要求的绝佳机会。与传统的2D设计相比,3D技术提供了更短的全局互连,更高的性能,更低的功耗,更高的包装密度和更小的占位面积以及低成本的混合技术功能。然而,在发展成可行的商业产品之前,3D IC提出了一些挑战。首先,没有商用的3D电气设计自动化(EDA)工具来支持3D IC设计。其次,缺乏确保3D IC正确功能的测试和验证工具及方法。第三,在架构级别进行设计空间探索对于充分利用3D集成至关重要。因此,随着3D体系结构的制造变得可行,迫切需要开发相应的3D EDA工具和3D测试方法,以供设计师探索3D IC设计空间并在体系结构级别评估3D效益。通过探索五个领域来应对3D IC面临的建筑探索挑战。首先,分析3D IC的层间连接的电气特性。该评估对于3D IC的时序分析和更好的系统设计至关重要。其次,提出了基于OpenAccess(OA)平台的3D IC设计流程。第三,我们解决了3D IC中的扫描链排序和优化问题。第四,讨论了基于内核的3D片上系统(SOC)的测试访问机制(TAM)优化。最后,在2D和3D空间中探索了结合了传统SRAM和几种新兴的非易失性存储技术的混合缓存体系结构。

著录项

  • 作者

    Wu, Xiaoxia.;

  • 作者单位

    The Pennsylvania State University.;

  • 授予单位 The Pennsylvania State University.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 141 p.
  • 总页数 141
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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