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Wafer level electrical test for optical proximity correction and/or etch bias
Wafer level electrical test for optical proximity correction and/or etch bias
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机译:晶圆级电气测试,用于光学接近度校正和/或蚀刻偏置
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摘要
Three reference resistors of the same resistance and a test structure are connected in a circuit having a Wheatstone Bride design. The circuit is electrically coupled between an input and ground. A voltage applied at the input resulting in an electrical characteristic difference between two midpoints of the circuit indicates the need for corrective action with respect to a design of the test structure for either OPC or etch bias.
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