METHOD FOR ROBUST CLOCK TREE SYNTHESIS CONSIDERING NEGATIVE BIAS TEMPERATURE INSTABILITY AND SUPPLY VOLTAGE VARIATION

摘要

The clock tree synthesis method considering aging phenomenon and voltage variation according to an embodiment of the present invention includes a step of setting a gating probability of each buffer constituting a clock tree, a step of calculating a signal probability of each buffer based on a gating probability Calculating a power supply voltage to be supplied to the buffer according to the calculated signal probability, and inserting the buffer by determining the position of the buffer.