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Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling

机译：使用投影扫描线采样的过程变化稳健和低功耗零偏斜缓冲时钟树综合

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1. Process-Variation Resilient and Voltage-Scalable DCT Architecture for Robust Low-Power Computing [J] . Karakonstantis G., Banerjee N., Roy K. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on . 2010,第10期

机译：用于稳健的低功耗计算的过程变化弹性和电压可伸缩DCT架构
2. Fast Timing-Model Independent Buffered Clock-Tree Synthesis [J] . Shih X.-W., Chang Y.-W. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on . 2012,第9期

机译：快速时序模型独立的缓冲时钟树综合
3. A Fast and Robust Scan-Line Search Algorithm for Object-to-Image Projection of Airborne Pushbroom Images [J] . Shen Xiang, Wu Guofeng, Sun Ke, Photogrammetric Engineering & Remote Sensing: Journal of the American Society of Photogrammetry . 2015,第7期

机译：一种快速鲁棒的扫描线搜索算法，用于机载手推扫帚图像的对象到图像投影
4. Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling [C] . Jeng-Liang Tsai, Chung-Ping Chen, C. . 2005

机译：使用投影扫描线采样的过程变化鲁棒且低功耗零偏缓冲时钟树合成
5. A METHODOLOGY FOR THE SYNTHESIS OF ROBUST CONTROL SYSTEMS FOR MULTIVARIABLE SAMPLED - DATA PROCESSES. [D] . ZAFIRIOU, EVANGHELOS. 1987

机译：用于多采样数据过程的鲁棒控制系统的综合方法。
6. A Robust Variable Sampling Time BLDC Motor Control Design Based upon μ-Synthesis [O] . Chung-Wen Hung, Jia-Yush Yen 2013

机译：基于μ综合的鲁棒可变采样时间BLDC电机控制设计
7. Process-variation resilient and voltage-scalable dct architecture for robust low-power computing [O] . Karakonstantis G., Banerjee N., Roy K. 2010

机译：具有过程变化的弹性和电压可缩放的DCT架构，可实现强大的低功耗计算

Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling

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