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Polymer film stencil process for fan-out wafer-level packaging of semiconductor devices

机译:聚合物薄膜模板工艺用于扇出半导体器件的晶圆级封装

摘要

The present invention provides stencil-based processes for fan-out wafer-level packaging (“FOWLP”) that addresses the limitations associated with prior art over-molding of dies. In the inventive process, a temporary carrier is coated with a release layer and curable adhesive backing layer. A die stencil film is then laminated to the coated carrier, and the dies are placed inside pre-formed cavities created in the laminated stencil. The gaps between the dies and the stencil are filled with a curable polymeric material, and a redistribution layer is constructed according to conventional processes. This process results in better repeatability, lower bowing in the carrier, and enhanced downstream processing.
机译:本发明提供了用于扇出晶片级封装(“ FOWLP”)的基于模板的工艺,其解决了与模具的现有技术的包覆成型相关的限制。在本发明的方法中,临时载体涂覆有剥离层和可固化的粘合剂背衬层。然后将模具模版膜层压到涂覆的载体上,并将模具置于层压模版中形成的预成型腔内。模具和模板之间的间隙填充有可固化的聚合物材料,并且根据常规工艺构造了再分配层。此过程可导致更好的可重复性,降低载体的弯曲度并增强下游加工效果。

著录项

  • 公开/公告号US10617010B2

    专利类型

  • 公开/公告日2020-04-07

    原文格式PDF

  • 申请/专利权人 BREWER SCIENCE INC.;

    申请/专利号US201715689056

  • 发明设计人 TONY D. FLAIM;

    申请日2017-08-29

  • 分类号H01L23/02;H05K3/12;H05K1/18;H05K1/02;H05K1/03;H01L23/13;H01L23/538;

  • 国家 US

  • 入库时间 2022-08-21 11:26:02

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