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Advanced modeling of planarization processes for integrated circuit fabrication

机译:用于集成电路制造的平坦化工艺的高级建模

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摘要

Planarization processes are a key enabling technology for continued performance and density improvements in integrated circuits (ICs). Dielectric material planarization is widely used in front-end-of-line (FEOL) processing for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to physically model and characterize the non-uniformities in the CMP process. To characterize polishing mechanisms at different length scales, physical CMP models are developed in three levels: wafer-level, die-level and particle-level. The wafer-level model investigates the CMP tool effects on wafer-level pressure non-uniformity. The die-level model is developed to study chip-scale non-uniformity induced by layout pattern density dependence and CMP pad properties. The particle-level model focuses on the contact mechanism between pad asperities and the wafer. Two model integration approaches are proposed to connect wafer-level and particle-level models to the die-level model, so that CMP system impacts on die-level uniformity and feature size dependence are considered. The models are applied to characterize and simulate CMP processes by fitting polishing experiment data and extracting physical model parameters. A series of physical measurement approaches are developed to characterize CMP pad properties and verify physical model assumptions. Pad asperity modulus and characteristic asperity height are measured by nanoindentation and microprofilometry, respectively. Pad aging effect is investigated by comparing physical measurement results at different pad usage stages. Results show that in-situ conditioning keeps pad surface properties consistent to perform polishing up to 16 hours, even in the face of substantial pad wear during extended polishing. The CMP mechanisms identified from modeling and physical characterization are applied to explore an alternative polishing process, referred to as pad-in-a-bottle (PIB). A critical challenge related to applied pressure using pad-in-a-bottle polishing is predicted.
机译:平面化工艺是使集成电路(IC)持续性能和密度提高的关键技术。介电材料平面化已广泛用于设备隔离的前端(FEOL)处理和用于互连的后端(BEOL)处理。本文研究了使用化学机械抛光(CMP)进行平面化的物理机理和变化。这项工作的主要成就和贡献是对CMP过程中的不均匀性进行物理建模和表征的系统方法。为了表征不同长度尺度的抛光机制,物理CMP模型分为三个级别:晶圆级别,芯片级别和粒子级别。晶圆级模型研究了CMP工具对晶圆级压力不均匀性的影响。开发了管芯级模型以研究由布局图案密度依赖性和CMP焊盘特性引起的芯片级不均匀性。粒子级模型专注于焊盘粗糙与晶圆之间的接触机制。提出了两种模型集成方法,将晶圆级和粒子级模型连接到芯片级模型,从而考虑了CMP系统对芯片级均匀性和特征尺寸依赖性的影响。通过拟合抛光实验数据并提取物理模型参数,这些模型可用于表征和模拟CMP工艺。开发了一系列物理测量方法来表征CMP焊盘特性并验证物理模型假设。垫的粗糙模量和特征粗糙高度分别通过纳米压痕法和微轮廓线法测量。通过比较不同垫使用阶段的物理测量结果来研究垫的老化效果。结果表明,即使面对长时间抛光过程中发生的严重磨损,原位修整仍可保持抛光垫表面性能始终如一,长达16小时。通过建模和物理表征确定的CMP机制可用于探索另一种抛光工艺,称为瓶中垫(PIB)。预测了与使用瓶中抛光法施加压力有关的关键挑战。

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