Fabrication technology for high-density Josephson integrated circuits using mechanical polishing planarization

摘要

A mechanical polishing planarization (MPP) process is developed with an endpoint detection method. MPP makes it possible to form self-aligned contacts on small junctions and to decrease parasitic inductance. It can also control the thickness of the insulation layers precisely. MPP was used to fabricate a 22 /spl mu/m/spl times/22 /spl mu/m vortex transitional memory cell and the cell operated correctly. The reliability of interlayer insulation was increased for 64-Kbit memory cell arrays fabricated using MPP. It is concluded that MPP is an effective technology for fabricating high-density Josephson circuits.