This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18 u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9 V supply voltage, has gate voltage of 0.45 V and consumes 102.07 muW power. The second circuit is designed partly using Dynamic Threshold-Voltage MOSFET (DTMOS) transistors with the aim to minimize power consumption. It runs on 0.7 V supply and has gate voltage of 0.35 V. The DTMOS approach is implemented on the 128-bit ROM core and in the pull up circuit of the column decoder. The latter ROM circuitpsilas power consumption is 38.93 muW, 61.86% less than the former, at the expenses of larger die area due to the usage of deep n-well process. The standard and DTMOST circuits have the die areas of 0.139 mum2 and 0.235 mum2, respectively.
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机译：本文研究了在Silterra 0.18 u CMOS工艺上实现的两个128位ROM电路的性能。第一个电路使用标准NMOS晶体管构建，在0.9 V的电源电压下运行，栅极电压为0.45 V，功耗为102.07μW。第二电路部分使用动态阈值电压MOSFET（DTMOS）晶体管设计，旨在最大程度地降低功耗。它采用0.7 V电源供电，栅极电压为0.35V。DTMOS方法在128位ROM内核和列解码器的上拉电路中实现。后一种ROM电路的功耗为38.93μW，比前者降低61.86％，这是由于使用了深n阱工艺而导致更大的芯片面积。标准电路和DTMOST电路的管芯面积分别为0.139 mum2和0.235 mum2。
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