Delay faults are an increasingly important test challenge. Traditional delay faultmodels are incomplete in that they model only a subset of delay defect behaviors. Tosolve this problem, a more realistic delay fault model has been developed which modelsdelay faults caused by the combination of spot defects and parametric process variation.According to the new model, a realistic delay fault coverage metric has been developed.Traditional path delay fault coverage metrics result in unrealistically low fault coverage,and the real test quality is not reflected. The new metric uses a statistical approach and thesimulation based fault coverage is consistent with silicon data. Fast simulation algorithmsare also included in this dissertation.The new metric suggests that testing the K longest paths per gate (KLPG) has highdetection probability for small delay faults under process variation. In this dissertation, anovel automatic test pattern generation (ATPG) methodology to find the K longesttestable paths through each gate for both combinational and sequential circuits ispresented. Many techniques are used to reduce search space and CPU time significantly.Experimental results show that this methodology is efficient and able to handle circuits with an exponential number of paths, such as ISCAS85 benchmark circuit c6288.The ATPG methodology has been implemented on industrial designs. Speed binninghas been done on many devices and silicon data has shown significant benefit of theKLPG test, compared to several traditional delay test approaches.
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