Survey of Fault Simulation, Fault Grading and Test Pattern Generation Techniques with Emphasis on the Feasibility of VHDL Based Fault Simulation.

摘要

The primary purpose of this report is to determine the state-of-the-art for fault simulators which are used to estimate the test coverage for the DUT. It is envisioned that the state-of-the-art survey will be used to assist in defining the fault simulation techniques which are applicable to VHDL models. The goal is to fully understand the current fault simulation state-of-the-art so that existing techniques can be used to assist in the design of a VHDL-based fault simulation tool. One attribute which defines a VHDL-based simulator is that a VHDL compliant simulator is used to simulate the faulty device. Hierarchical serial fault simulation and hierarchical concurrent fault simulation are two techniques which can be used to develop a VHDL-based fault simulator. The state-of-the-art for fault grading techniques along with an overview of TPG methods is also provided in this report. While fault simulation is the main focus of this report, fault grading and TPG are included to completely describe the test generation, fault simulation, and fault grading process. It is important to realize that fault simulation is a means to assist TPG and estimate fault coverage via fault grading. The desired goal for a tool set is to contain a fault simulation technique which seamlessly augments the TPG process and performs fault grading in an efficient fashion.