Test generation for path delay faults based on test set for stuck-at faults

摘要

With the speed up of logic circuits, testing for correct operation at desired clock rates has heroine important. Especially, the development of a method for generating test-pairs for path delay faults is needed. It is difficult to generate the test-pair for each path, because the number of paths to test may he very large. In this paper, based on a test set for stuck-at faults we describe a method for generating several test-pairs in each of which a signal transition is propagated to at least one primary output from the output of the same one gate. Using the results of the path delay fault simulations with respect to the generated test-pairs we evaluate the effectiveness of the method in detecting singly-testable path delay faults [7].