Automatic Test Pattern Generation for Three-State Circuits

摘要

The main subject of this thesis is automatic test pattern generation (ATPG) forstructural production testing to detect single stuck-at faults (SSAFs) in combinational or scan-based digital logic circuits. Potential detection of SSAFs, and Iddq detection of SSAFs and bridging faults are considered as well. In particular, the authors investigate open questions related to ATPG for industrial circuits that contain three-state (3-state) structures in addition to the standard Boolean gates. The main contribution of this thesis consists of generalizing the various state-of-the-art algorithms and techniques in ATPG, from the domain of purely Boolean logic circuits to the domain of 3-state circuits with intentional and external restrictions. Specifically, the state-of-the-art algorithms and techniques in deterministic TPG and FS, as well as common ATPG preprocessors, have been adapted and extended in order to cover this domain. Moreover, two special forms: compact ATPG and circuit-partitioned ATPG, are also evaluated.