Reliability Analyses of a Surface Mounted Package Using Finite Element Simulation

摘要

The objective of this study was to evaluate a surface mounted leadless chip carrier to determine if it had met the critical requirements of proper heat dissipation, acceptable thermal stress levels and a minimum temperature rise in the die. Two finite element models were utilized. The first model represented the package/board assembly. This model was used to simulate the effects various die sizes, heat producing areas, and voids in the die attach and thermal undercoat on the package thermal resistance. The second model represented a leadless solder connection. The output temperature solutions from the package/board model were then used as input conditions for this solder connection model. Thermal stress simulations were performed on both models to determine if any of the stress values were too high. The results of these simulations were then compared to determine the correlation between changes in the package thermal resistance and stresses in the solder connection.