3-D finite elements simulation of drop test reliability on a Chip Scale Package: Focus on the component architecture and materials

摘要

Chip Scale Package (CSP) fulfills the demand for small, light and portable handheld electronic devices and is one of the most advanced packaging concepts. Reliability of this package becomes more critical since their solder joins endure harsh mechanical loads such as drop impact during transportation or operations. Cracking of solder interconnections is often caused by excessive bending of circuit board subject to input acceleration created from dropping handled electronic products. It is known that the dynamic strains and stress states of solder bumps directly affect their reliability during drop impact.