SCMOS (Scalable Complementary Metal Oxide Silicon) Silicon Compiler Organelle Design and Insertion

摘要

Conversion of the MacPitts Silicon Compiler from NMOS to Scalable CMOS technology includes the custom design of SCMOS organelles to replace the NMOS organelles in the data-path. Three arithmetic organelles, the incrementor, decrementor and subtractor, are designed using the Magic layout editor. Cell insertions are made to the MacPitts Silicon Compiler installed on ISI workstations. The MacPitts Silicon Compiler translates the low level functional descriptions of a circuit into a computer readable mask level description which can then be sent to a vendor for fabrication. It was developed at the Massachusetts Institute of Technology Lincoln Laboratories. It is a fixed floor plan compiler, with an N-type Metal Oxide Silicon (NMOS) technology dependent design, based on the graphics layout editor Caesar. The effort of the Silicon Compiler Group at the Naval Postgraduate School involves the conversion of the NMOS based MacPitts to Scalable Complementary Metal Oxide Silicon (SCMOS) technology. SCOMS technology has the advantages of smaller feature size and lower power consumption.