Processing-Enhanced SEU Tolerance in High Density SRAMs

摘要

We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandia's 2-micron-technology 16K SRAMs are fabricated with a radiation-hardened 1-micron CMOS process. An advanced two-dimensional transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the 2-micron process to the 1-micron process. Error cross-section data, performed at the Berkeley cyclotron on the first such device lot, indicate that total improvement in threshold LET is a factor of 2 or better. A saturation phenomenon associated with the high-LET events is described, and physical mechanisms responsible for the saturation are discussed. (RH)