Compact Self-Aligned Ion Implantation Transistor Edge Resistor for SEU Mitigation in SRAM

摘要

This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well (36) covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator (32) and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor (20) on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator (50) adjacent to the resistor, removing the barrier, and forming a gate layer (52) on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.