Utilization of an Electronic Circuit Simulator in CMOS Latch-Up Studies.

摘要

The 2-D device simulator presented in this work allows the investigation of the effect of ionizing radiation dose rate on the performance of CMOS circuits. The simulator is composed of two parts, a diffusion current module and a lumped-element module. The first module solves the current transport equations with the aid of the HSPICE code. The lumped-element module then simulates the electrical characteristics of the parasitic pnpn structure (present in CMOS circuits) using the results from the first module as input parameters. The model was applied to study the latch-up vulnerability of a CMOS inverter as a function of circuit layout and distribution of substrate contacts. Results of radiation hardening efforts are presented.