CMOS工艺中抗闩锁技术的研究

摘要

伴随着CMOS工艺技术的发展，CMOS电路已经成为VLSI制造中的主流，而CMOS器件特征尺寸的快速缩小和CMOS电路的广泛应用，使得CMOS电路中的latch-up效应引起的可靠性问题也越来越受到大家的重视。阐述了CMOS工艺中闩锁的概念、原理及其给电路的可靠性带来的严重后果，深入分析了产生闩锁效应的条件、触发方式，并针对所分析的闩锁原因从版图设计、工艺改良、电路应用三个方面提出了一些防闩锁的优化措施，以满足和提高CMOS电路的可靠性要求。%With the development of CMOS process technology, CMOS VLSI circuit manufacturing has become mainstream, and widely applied rapidly reduced feature sizes in CMOS devices and the CMOS circuit, a CMOS circuit so that the reliability of the effect caused by the latch-up increasingly attentions. The paper described the concept of latch CMOS process, the serious consequences of the generation of latch-up condition, the way conflict with the law, and the reasons for the latch from the layout analysis, process improvement, three circuit applications made some latch optimization measures to meet the requirements and improve the reliability of CMOS circuits.